IPC China, Shanghai, October 10, 2012 - IPC - International Electronics Industry Association? Released Chinese version of IPC/JEDEC-9704 Printed Circuit Assembly Strain Gage Test Guideline (Revised Edition) A). When the joint between the printed circuit board and the electronic component is under tremendous pressure, problems may arise: from the rupture of the solder ball to the damage of the conductor and the crater of the pad. Stress testing is a challenge for EMS and OEM companies, and the latest joint industry guidance allows engineers to easily perform stress tests during production.
"Rev. A aims to determine a common method for measuring strain on printed circuit assemblies due to circuit board distortion." said Jagadeesh Radhakrishnan, reliability engineer at Intel Corp., who led the IPC SMT placement reliability test method. The working group revised this test guide. “The first edition provided the industry with the criteria for qualifying/nonconforming points, while revision A,” as Radhakrishnan said, “...redirects the focus to providing a method. The guide does not set goals, and Is a detailed explanation of how stress measurements are made."
Revision A provides a formula for calculating stress and elaborates techniques for analyzing test data. These tests can be performed at various stages in the production of a printed circuit board assembly. Components can be tested during assembly or factory testing, and can also be tested before the package is shipped.
“Besides the change in focus, IPC/JEDEC-9704A-CN has also expanded its scope: it has added recommendations for sockets and ceramic capacitors; previous documents only addressed ball grid arrays (BGAs). Radhakrishnan added, "The guide also revise some of the parameters of the in-circuit test fixture and provide the best design practices to reduce the problems faced by users."