The center hole of the pad is slightly larger than the diameter of the device lead. The pad is too large to form a false weld. The pad outer diameter D is generally not less than (d+1.2) mm, where d is the lead aperture. For high density digital circuits, the minimum diameter of the pad can be (d+1.0) mm.
PCB and circuit anti-jamming measures
The anti-jamming design of the printed circuit board has a close relationship with the specific circuit. Here I will give some explanations on several commonly used measures for PCB anti-jamming design.
1. Power line design
According to the size of the printed circuit board current, try to increase the width of the power cord to reduce loop resistance. At the same time, the direction of power lines and ground lines and the direction of data transfer are consistent, which helps to enhance anti-noise capability.
2. Ground design
The principle of ground design is:
(1) Separated digitally from simulated ground. If there are both logic circuits and linear circuits on the board, they should be separated as much as possible. The ground of the low-frequency circuit should be connected with a single point as much as possible, and when the actual wiring is difficult, the partial connection can be connected in series. The high-frequency circuit should adopt multi-point series grounding, the ground line should be short and rent, high-frequency components around the grid as much as possible to a large area of the foil.
(2) The grounding wire should be as thick as possible. If the grounding wire uses a very thrilling line, the grounding potential changes with the change of the current, so that the anti-noise performance is reduced. Therefore, the ground wire should be thickened so that it can pass three times the allowable current on the printed board. If possible, the grounding wire should be 2~3mm above.
(3) The ground wire constitutes a closed loop. A printed circuit board consisting of only digital circuits may have a resistance to noise due to the fact that the grounding circuit is formed into a group loop.
3. Back-fat capacitor configuration
One of the common practices in PCB design is to configure appropriate decoupling capacitors at various critical points on the printed board.
The general configuration principle of the retraction capacitor is:
(1) The input terminal of the power supply is connected with an electrolytic capacitor of 10~100uf. If possible, it is better to use 100uF or more.
(2) In principle, each integrated circuit chip should be equipped with a ceramic capacitor of 0.01pF. If the gap of the printed circuit board is not enough, a capacitance of 1~10pF can be arranged for every 4~8 chips.
(3) For devices with weak noise immunity and large power supply changes during turn-off, such as RAM and ROM memory devices, a tantalum capacitor should be directly connected between the power line and the ground of the chip.
(4) Capacitor leads must not be too long, especially high-frequency bypass capacitors cannot have leads.
In addition, we should also pay attention to the following two points:
(1) When there are contactors, relays, buttons and other components in the printed board. When operating them, large spark discharges will occur, and the RC circuit shown in the figure must be used to absorb the discharge current. Generally R takes 1~2K, C takes 2.2~47UF.
(2) The input impedance of CMOS is very high, and it is susceptible to induction. Therefore, the unused terminal must be grounded or connected to a positive power supply.